The present disclosure relates to a driving method of a solid-state imaging apparatus and a camera system, which efficiently discharges a signal charge accumulated in a photoelectric transducer having a large capacity.
In related art, a CMOS (Complementary Metal Oxide Semiconductor) image sensor uses a reset transistor for operating a CDS (Correlated Double Sampling) circuit, which removes noise from a pixel signal. Also, a shutter operation is performed which discharges a signal charge accumulated in a photoelectric transducer (for example, a photodiode), which is arranged at an arbitrary position different from that of a readout row (or column, or pixel). In the following description, a CMOS image sensor is abbreviated to CIS (CMOS Image Sensor), and a photodiode is abbreviated to PD (Photo Diode).
Further, a configuration and operation example of a general CIS is disclosed in Japan Patent No. 4048415. Here, a configuration and operation example of a CIS 100 from the related art will be described.
FIG. 10 is a circuit diagram which shows a configuration example of the CIS 100 from the related art.
The CIS 100 includes a pixel section 101 and a CDS section 102.
The pixel section 101 includes 4 types of MOS transistors (transfer transistor Tr1, reset transistor Tr2, amplification transistor Tr3, and selection transistor Tr4) constituting a PD, which is a photoelectric transducer, and a readout circuit of the PD. Here, a gate which the transfer transistor has is referred to as a transfer gate, and the gates of the other transistors are referred to in a similar way. Further, the pixel section 101 includes a floating diffusion section (hereinafter, a FD (Floating Diffusion) section) which is a floating diffusion region.
The PD generates a signal charge corresponding to the amount of received light, and the transfer transistor Tr1 transfers the signal charge of the PD to the FD section, based on a transfer pulse.
The reset transistor Tr2 regularly resets the voltage of the FD section to the power supply voltage Vdd, based on a gate drive pulse which turns on the reset gate. The voltage value of this Vdd is, for example, 1.8V or 2.7V, and when the pixels increase in size, 5V may also be used.
The amplification transistor Tr3 outputs an output signal corresponding to a voltage fluctuation of the FD section connected to this gate.
The selection transistor Tr4 outputs the output signal of the amplification transistor Tr3 to a vertical signal line, based on a selection pulse which selects the pixel row.
A vertical signal line is arranged in each pixel column, and one end is connected to a load transistor Tr5, which is used as a constant current source outside an imaging region. Further, the other end of the vertical signal line is connected to a signal processing circuit, which is arranged in each pixel column outside the imaging region. This image processing circuit includes the CDS section 102, and outputs an imaging signal by performing various signal processes to the pixel signal arranged in the next stage of the imaging region.
The CDS section 102 includes transistors Tr6 and Tr7 which use SHR and SHS as gate signals, capacitors with electrostatic capacities of Cs and Cr, a differential amplifier which obtains a difference value between the level of the output signals, and a transistor Tr8 arranged between the differential amplifier and a horizontal signal line. This CDS section 102 is a circuit which outputs a signal proportional to the difference between two signals input in a time series.
Here, an operation example of the CIS 100 will be described.
First, the CIS 100 performs a shutter operation which begins the accumulation of a signal charge for an arbitrary row (shutter row, column, or pixel). The pixel section 101, which has become a shutter row, turns on the reset gate and the transfer gate at the same time, and discharges all of the signal charge accumulated in the PD to a power supply drain. The signal charge is discharged, and the PD, which has become empty, starts the accumulation of a signal charge when the transfer gate is turned on again.
Afterwards, when a fixed time has elapsed, a readout operation is performed for an arbitrary line desired to finish the accumulation of the signal charge. The selection gate of the selection transistor is turned on in order to select a signal line which performs a connection to the CDS section 102 at the row (readout row, column, or pixel) to which this readout operation is performed. Afterwards, a signal output when the reset gate is sequentially turned on, and a signal output when the transfer gate is turned on, are both read out by turning on the SHS gate and turning on the SHR gate of the CDS section 102. In this case, when the transistor Tr6 is turned on by a timing signal SHS at the time when the signal charge of the PD is accumulated in the FD section, the capacitor Cs holds the output signal. On the other hand, when the transistor Tr7 is turned on by a timing signal SHR at the time when the FD section is reset, the capacitor Cr holds the output signal of the pixel section 101.
Afterwards, the CDS section 102 treats the signal output when the reset gate is turned on as a noise level, and treats the signal output when the transfer gate is turned on as a noise level which has been superimposed. Also, the level of the output signals held in the two capacitors Cs and Cr are compared by the differential amplifier, the difference between them both is taken, and a difference value is output to the horizontal signal line through the transistor Tr8. In this case, a high quality image is obtained without noise, by excluding the noise level obtained from the difference between the signal output when the reset gate is turned on and the signal output when the transfer gate is turned on.
Further, a structure such as shown in JP 2001-45383A is known as technology related to a shutter operation of the related art, which varies an accumulation period of the signal charge, and reads out an arbitrary part of the pixel region. In addition, an outline of a configuration of a CIS from the related art is disclosed in JP 2006-310932A.